Hi,
There can be many possible physical memory layouts for OpenCL images. To accelerate the accessing of images, run-time can rearrange the data layout to take advantage of special hardware (say texture buffer) presents in the device. Most of the cases, applications access the images in tiled-manner. Many systems take advantage of this feature and try to map the image accordingly. However, the actual layout formats e.g. size of the tiles/blocks, arrangement of blocks etc. vary from device to device. Generally the translating from user address space to the tiled arrangement is transparent to the user. User may apply some known assumptions to extract the best performance. I refer you to check following sectionin AMD's OpenCL Optimization guide to get an idea.
Chapter 2 OpenCL Performance and Optimization for GCN Devices->2.8 Additional Performance Guidance->2.8.2 Memory Tiling
Regards,